![]() ![]() Nourbakhsh A, Zubair A, Sajjad R N, Tavakkoli K G A, Chen W, Fang S, Ling X, Kong J, Dresselhaus M S, Kaxiras E, Berggren K K, Antoniadis D, Palacios T 2016 Nano Lett. Yang L, Lee R T P, Ra S S P, Tsai W, Ye P D 2015 2015 73rd Annual Device Research Conference ( DRC), Columbus, OH, USA, June 21–24, 2015 p237 Lingming Y, Kausik M, Yuchen D, Han L, Heng W, Hatzistergos M, Hung P Y, Robert T, Wilman T, Chris H, Peide D Y 2014 2014 Symposium on VLSI Technology Digest of Technical, Honolulu, HI, USA, June 9–12, 2014 p1 Xie L, Liao M, Wang S, Yu H, Du L, Tang J, Zhao J, Zhang J, Chen P, Lu X, Wang G, Xie G, Yang R, Shi D, Zhang G 2017 Adv. Nourbakhsh A, Zubair A, Huang S, Ling X, Dresselhaus M S, Kong J, De Gendt S, Palacios T 2015 2015 Symposium on VLSI Technology Digests of Technical Kyoto, Japan, June 16–18, 2015 p28 6 147 Google Scholarĭesai S B, Madhvapathy S R, Sachid A B, Llinas J P, Wang Q, Ahn G H, Pitner G, Kim M J, Bokor J, Hu C, Wong H P, Javey A 2016 Science 354 99 Google Scholar Radisavljevic B, Radenovic A, Brivio J, Giacometti V, Kis A 2011 Nat. 1 16052 Google ScholarĪkinwande D, Huyghebaert C, Wang C H, Serna M I, Goossens S, Li L J, Wong H P, Koppens F H L 2019 Nature 573 507 Google Scholar 9 768 Google ScholarĬhhowalla M, Jena D, Zhang H 2016 Nat. Uchida K, Watanabe H, Kinoshita A, Koga J, Numata T, Takagi S 2002 Experimental Study on Carrier Transport Mechanism in Ultrathin-body SOI n and p-MOSFETs with SOI Thickness Less than 5 nm (IEEE), San Francisco, CA, USA, December 8–11 2002 p47įiori G, Bonaccorso F, Iannaccone G, Palacios T, Neumaier D, Seabaugh A, Banerjee S K, Colombo L 2014 Nat. Liu Y, Duan X, Shin H J, Park S, Huang Y, Duan X 2021 Nature 591 43 Google Scholar Sakaki H, Noda T, Hirakawa K, Tanaka M, Matsusue T 1987 Appl. This method can be used to rapidly screen two-dimensional materials that are immune to short-channel effects and also are suitable for the fabrication of high-performance FETs.ĭas S, Sebastian A, Pop E, McClellan C J, Franklin A D, Grasser T, Knobloch T, Illarionov Y, Penumatcha A V, Appenzeller J, Chen Z H, Zhu W J, Asselberghs I, Li L J, Avci U E, Bhat N, Anthopoulos T D, Singh R 2021 Nat. The on/off ratio is greater than 10 7 and the off-state current is less than 100 fA/μm under different source-drain voltages, which are immune well to the direct source-to-drain tunneling effect. The 8-nm spacer transistor exhibits good switching characteristics. Here we report a method of stably fabricating vertical short-channel MoS 2 FETs by using graphene as the contact material and h-BN as the spacer. Owing to the difficulty in obtaining channel lengths below 10 nm for 2D materials, there are few stable methods of fabricating short channel 2D semiconductor FETs. Field effect transistors (FETs) based on two-dimensional (2D) materials have great potential applications in very large-scale integration technology, and high-performance short channel 2D semiconductor FETs are essential. ![]()
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |